Compile code for the processor in mips16 mode.
The -mentry option tells the compiler to use the entry and exit pseudo-instructions for function entry and exit. The pseudo-instructions save and restore registers at function entry and exit. These work by triggering an unimplemented instruction trap. Your exception handler must handle these instructions correctly. This is a time/space tradeoff; code using the entry and exit instructions is smaller, but takes longer to execute.
Any MIPS configuration of the compiler can select big-endian or little-endian output at run time. Use -EB to select big-endian output and -EL for little-endian. If neither -EL nor -EB are defined, big-endian is the default.
Do not depend on the order of the registers shown in Register allocation definitions. Instead, use GCCs asm( ) extension and allow the compiler to schedule registers.

The compiler always allocates space on the stack for all arguments even when some or all of the arguments to a function are passed in registers. This stack space is a large enough structure to contain all the arguments. After promotion and structure return pointer insertion, the arguments are aligned according to normal structure rules. Locations used for arguments within the stack frame are referred to as the home locations. Whenever possible, arguments declared in variable argument lists, as with those defined using a `va_list' declaration, are passed in the integer registers, even when they are floating-point numbers.
If the first argument is an integer, remaining arguments are passed in the integer registers.
The compiler passes structures and unions as if they were very wide integers with their size rounded up to an integral number of words. The "fill bits" necessary for rounding up are undefined. A structure can be split so that a portion is passed in registers and the remainder passed on the stack. In this case, the first words are passed in `$4', `$5', `$6', and `$7' as needed, with additional words passed on the stack.
The rules for assigning which arguments go into registers and which arguments must be passed on the stack can be explained by considering the list of arguments itself as a structure, aligned according to normal structure rules. Mapping of this structure into the combination of registers and stack is as follows; everything with a structure offset greater than or equal to 32 is passed on the stack. The remainder of the arguments are passed in `$4..$7' based on their structure offset. Any holes left in the structure for alignment are unused, whether in registers or on the stack.
The caller to a function that returns a structure or a union passes the address of an area large enough to hold the structure in register `$4'. The function returns a pointer to the returned structure in register `$2'.
Assemble code for the processor in mips16 mode.
Any MIPS configuration of the assembler can select big-endian or little-endian output at run time.Use `-EB' to select big-endian output, and `-EL' for little-endian. The default is big-endian.
For information about the MIPS instruction set, see MIPS RISC Architecture (Kane and Heindrich, Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same volume.
There are 32 64-bit general (integer) registers, named `$0..$31'. There are 32 64-bit floating point registers, named `$f0..$f31'.
Link objects for the processor in little endian mode.
Link objects for the processor in big-endian mode.
/* The following TEXT start address leaves space for the monitorworkspace. */ENTRY(_start)OUTPUT_ARCH("mips:4000")OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")GROUP(-lc -llsi -lgcc)SEARCH_DIR(.)__DYNAMIC = 0;/** Allocate the stack to be at the top of memory, since the* stack grows down*/PROVIDE (__stack = 0);/* PROVIDE (__global = 0); *//** Initalize some symbols to be zero so we can reference them* in the crt0 without core dumping. These functions are all* optional, but we do this so we can have our crt0 always use* them if they exist. This is so BSPs work better when using* the crt0 installed with gcc. We must initalize them twice,* so we multiple object file formats, as some prepend an* underscore. */PROVIDE (hardware_init_hook = 0);PROVIDE (software_init_hook = 0);SECTIONS{. = 0xA0020000;.text : {_ftext = . ;*(.init)eprol = .;*(.text)PROVIDE (__runtime_reloc_start = .);*(.rel.sdata)PROVIDE (__runtime_reloc_stop = .);*(.fini)etext = .;_etext = .;}. = .;.rdata : {*(.rdata)}_fdata = ALIGN(16);.data : {*(.data)CONSTRUCTORS}. = ALIGN(8);_gp = . + 0x8000;__global = _gp;.lit8 : {*(.lit8)}.lit4 : {*(.lit4)}.sdata : {*(.sdata)}edata = .;_edata = .;_fbss = .;.sbss : {*(.sbss)*(.scommon)}.bss : {_bss_start = . ;*(.bss)*(COMMON)}end = .;_end = .;}
mips-lsi-elf-gdb prog
GDB is free software and . . .
(gdb)target lsi /dev/ttyb
(gdb)load prog
(gdb)run
On PC platforms, substitute the specific COM port:
C:\> mips-lsi-elf-gdbprog
GDB is free software and . . .
(gdb)target lsi com3
(gdb)load prog
(gdb)run
For this to be useful, you must know something about the MIPS debugging protocol, also called `rmtdbg'. An informal description can be found in the GDB source files, specifically in the `remote-mips.c' file .You can see some debugging information about communications with the board by setting the `remotedebug'variable. If you set it to 1 using the `set remotedebug 1' command, every packet is displayed. If you set it to 2, every character is displayed. You can check the current value at any time with the `showremotedebug' command.
You can control the timeout used while waiting for a packet, in the MIPS debugging protocol, with the `set timeout seconds' command. The default is 5 seconds. Similarly, you can control the timeout used while waiting for an acknowledgment of a packet with the set retransmit-timeout seconds command. The default is 3 seconds. You can inspect both values with the `show timeout' and `show retransmit-timeout' commands.
C:\>mips-lsi-elf-run -t hello.xbC:\>
2 a0020000 ; width 4 ; load instruction2 a0020004 ; width 4 ; load instruction2 a0020008 ; width 4 ; load instruction2 a002000c ; width 4 ; load instruction2 a0020010 ; width 4 ; load instruction2 a0020014 ; width 4 ; load instruction2 a0020018 ; width 4 ; load instruction2 a002001c ; width 4 ; load instruction2 a0020020 ; width 4 ; load instruction2 a0020024 ; width 4 ; load instruction. . .
%mips-lsi-elf-run -v hello.xbmips-lsi-elf-run helloHello, world!3 + 4 = 7MIPS 32-bit simulatorBig endian memory model0x00200000 bytes of memory at 0xa0000000Instruction fetches = 4138Pipeline ticks = 4138
%mips-lsi-elf-run -v -m 200000 hello.xbmips-lsi-elf-run helloHello, world!3 + 4 = 7MIPS 32-bit simulatorBig endian memory model0x00040000 bytes of memory at 0xa0000000Instruction fetches = 4138Pipeline ticks = 4138
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