Contents|Index|Previous|Next Hitachi SH dependent features See the following documentation for the Hitachi SH architecture’s features and options for the assembler. Options for SH Syntax for SH Special characters for SH Register names for SH Addressing modes for SH Floating point for SH Machine directives for SH Opcodes for SH Options for SH as has no additional command-line options for the Hitachi SH family. Syntax for SH The following documentation refers to the syntax for the Hitachi SH. Special characters for SH ! is the line comment character. You can use ; instead of a newline to separate statements. Since $ has no special meaning, you may use it in symbol names. Register names for SH You can use the predefined symbols ‘r0’, ‘r1’, ‘r2’, ‘r3’, ‘r4’, ‘r5’, ‘r6’, ‘r7’, ‘r8’, ‘r9’, ‘r10’, ‘r11’, ‘r12’, ‘r13’, ‘r14’, and ‘r15’ to refer to the SH registers. The SH also has the following control registers. pr Procedure register (holds return address) pc Program counter mach macl High and low multiply accumulator registers sr Status register gbr global Base register vbr Vector base register (for interrupt vectors) Addressing modes for SH as understands the following addressing modes for the SH. Rn in the following refers to any of the numbered registers, but not the control registers. Rn Register direct @Rn Register indirect @-Rn Register indirect with pre-decrement @Rn+ Register indirect with post-increment @(disp, Rn) Register indirect with displacement @(R0, Rn) Register indexed @(disp, GBR) GBR offset @(R0, GBR) GBR indexed addr @(disp, PC) PC relative address (for branch or for addressing memory) The as implementation allows you to use the simpler form, addr, anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers. #imm Immediate data Floating point for SH The SH family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools. Machine directives for SH as has no machine-dependent directives for the SH. Opcodes for SH For detailed information on the SH machine instruction set, see SH-Microcomputer User’s Manual (Hitachi Micro Systems, Inc.). as implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that because as supports a simpler form of PC-relative addressing, you may simply use  (for example) the following declaration. mov.l bar,r0 Other assemblers might require an explicit displacement to bar from the program counter: mov.l @(disp, PC) Top|Contents|Index|Previous|Next