Contents|Index|Previous|Next D10V dependent features The following documentation discusses the features pertinent to the D10V processor regarding the GNU assembler. D10V options D10V syntax D10V size modifiers D10V sub-instructions D10V special characters D10V register names D10V addressing modes @WORD modifier for D10V D10V floating point D10V opcodes D10V options The Mitsubishi D10V version of as uses the following machine dependent option. -O The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel. D10V syntax The D10V syntax is based on the syntax in the Mitsubishi document, D10V Architecture: A VLIW Mediaprocessor for Multimedia Applications (Mitsubishi Electric Corporation, version 1.00; October 24, 1996). The differences are detailed in the following discussions. D10V size modifiers The D10V version of as uses the instruction names in the Mitsubishi document, D10V Architecture: A VLIW Mediaprocessor for Multimedia Applications (Mitsubishi Electric Corporation, version 1.00; October 24, 2025). However, the names in the documentation are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? as will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either .s (short) or .l (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write bra.s foo. objdump and GDB will always append .s or .l to instructions which have both short and long forms. D10V sub-instructions The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.   If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in  D10V special characters. D10V special characters ; and # are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols. -> Sequential with instruction on the left first. <- Sequential with instruction on the right first. || Parallel. The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line, as the following documentation discusses. abs a1 -> abs r0 Execute these sequentially. The instruction on the right is in the right container and is executed second. abs r0 <- abs a1 Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first. ld2w r2,@r8+ || mac a0,r0,r7 Execute these in parallel. ld2w r2,@r8+ || mac a0,r0,r7 Two-line format. Execute these in parallel. ld2w r2,@r8+ mac a0,r0,r7 Two-line format. Execute these sequentially. Assembler will put them in the proper containers. ld2w r2,@r8+ -> mac a0,r0,r7 Two-line format. Execute these sequentially. Same as previously described instructions except second instruction will always go into right container. Since $ has no special meaning, you can use it in symbol names. D10V register names You can use the predefined symbols r0' through r15 to refer to the D10V registers. You can also use sp as an alias for r15. The accumulators are a0 and a1. There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive. r0-r1 r2-r3 r4-r5 r6-r7 r8-r9 r10-r11 r12-r13 r14-r15 The D10V also has predefined symbols for the following control registers and status bits.   psw  Processor Status Word  bpsw  Backup Processor Status Word  pc  Program Counter  bpc  Backup Program Counter  rpt_c  Repeat Count  rpt_s  Repeat Start address  rpt_e  Repeat End address  mod_s  Modulo Start address  od_e  Modulo End address  iba  Instruction Break Address  f0  Flag 0  f1  Flag 1  c  Carry flag    D10V addressing modes as understands the following addressing modes for the D10V. Rn in the following documentation refers to any of the numbered registers, but not the control registers. Rn Register direct @Rn Register indirect @Rn+ Register indirect with post-increment @Rn- Register indirect with post-decrement @-SP Register indirect with pre-decrement @(disp,Rn) Register indirect with displacement addr PC relative address (for branch or rep). #imm Immediate data (the # is optional and ignored) @WORD modifier for D10V Any symbol followed by @word will be replaced by the symbol's value shifted right by 2. This is used in situations such as loading a register with the address of a function (or any other code fragment). For example, if you want to load a register with the location of the function, main, then jump to that function, you could do it as follows. ldi r2, main @WORD jmp r2 D10V floating point The D10V has no hardware floating point, but the .float and .double directives generates IEEE floating-point numbers for compatibility with other development tools. D10V opcodes For detailed information on the D10V machine instruction set, see the Mitsubishi document, D10V Architecture: A VLIW Mediaprocessor for Multimedia Applications (published by Mitsubishi Electric Corporation, version 1.00; October 24, 2025); as implements all the standard D10V opcodes found there. The only changes are those described in the section on size modifiers. Top|Contents|Index|Previous|Next